SILICON THERMAL OXIDATION - WET OXIDATION CUSTOM PROCESSES Silicon thermal oxidation processes are available only for prime wafers, delivered in sealed containers [original manufacturer seal must be present] Wafers are RCA, SC1 - SC2, Dilute HF Dipped prior to final DI water rinse and spindry HTE LABS sputter deposition services, thin film vacuum deposition,wafer foundry, bipolar process development, contract R&D, bipolar wafer foundry services, thin film vacuum deposition services SILICON THERMAL OXIDATION WET OXIDATION xxxnm HTE Labs PROPERTIES / FEATURESAPPLICATIONS Chemical Composition=SiO2 Passivation of junctions, protection of silicon surface. Refractive Index=1.462 Gate dielectric for MOS FETS, dielectric for MOS Capacitors. Dielectric Constant=3.4 Masking layer during dopant predeposition and diffusion. Uniformity=5% to 10%Masking layer during Ion Implantation process. SiO2 Color chart and calculators HTE AN101Insulation between conductors and silicon surface. More properties @ HTE LABS APP NOTESEtch stop, sacrificial layer, Ion Implant screen layer, etc. SHORT PROCESS DESCRIPTION Silicon thermal oxidation processes are available only for prime wafers, delivered in sealed containers [original manufacturer seal must be present] Wafers are RCA, SC1 - SC2, Dilute HF Dipped prior to final DI water rinse and spindry. As a standard procedure, wafers are loaded in quartz tubes at 600C and are unloaded after a ramp down also at 600C. Silicon wet thermal oxidation is performed in an atmosphere of H2, O2 Pyrogenic generated steam. Minim temperature is 900C. WAFER FOUNDRY - R&D SEMICONDUCTOR PROCESS DEVELOPMENT HTE LABS is helping customers to solve R&D problems, capacity problems, lower cost as well as develop a back-up process for existing in-house operations. Any company currently involved or contemplating R&D related to semiconductor devices or thin film technologies, is encouraged to consider using HTE LABS expertise and capabilities. To contact HTE LABS and discuss an application in the strictest confidentiality, navigate to CONTACT PAGE. PROCESS ORDERING INFORMATION SI ORIENTATIONWAFER SIZE[mm] TEMPERATURE[C] THICKNESS[nm] TIME[hours] Select orientation[100][111] Select wafer size25 [1"]50 [2"]75 [3"]100 [4"]125 [5"]150 [6"]200 [8"]300 [12"] Select temperature800900950100010501100115012001250 Process parametter TIME is calculated using Stanford SUPREM 4 software for the <100> and <111> orientation and for low doping levels as the worst case scenario. Actual oxidation TIME may vary. HTE Labs whenever feasible is tailoring each process to the actual orientation and doping levels such that the end thickness is within specified tolerance. Due to these factors, for Wet Oxidation processes oxide thickness tolerance is +/-5% to 10%. STANDARD PROCESS PRICE LIST PROCESS CODEORIENTATIONWAFER SIZE[mm]TEMPERATURE[C]THICKNESS[nm]TIME[h]MINIM ORDERUNIT PRICE[$] [100][W100][WTOX1100C][xxxNM]1001001100xxx2.3512513.100 [111][W100][WTOX1100C][xxxNM]111100110010002.1952512.710 INSTANT QUOTE PROCESS CODE QTYEMAIL Minimum batch for thermal oxidation is 25 wafers and maximum is 50 wafers depending on the wafer size and equipment availability at the time of RFQ. ORDERING: Registered customers can order online from within assigned BUSINESS PORTAL. A copy of the order along with an order confirmation receipt is issued instantly for all orders placed on line. On line Orders have to be verified, accepted and acknowledged by HTE LABS sales department in writing before, becoming non cancelable binding contracts. DELIVERY: Typical delivery for Standard processes is 2-4 working days ARO. For Custom processes lead time may vary. HTE Labs may supply on request substrate materials from its own inventory or from third party supplier. SHIPPING & PACKING: For certain processes, customer should ship only prime wafers, delivered in sealed containers [original manufacturer seal must be present]. All wafers shipped to HTE LABS by customers, should be packed in suitable wafer carriers or wafer containers, wrapped in reusable minim 2 layers of air bubble packing material [pink anti-static bubble cushioning wrap], or air pillows and heavy wall cardboard boxes. Foam packing peanuts are not acceptable due to the nuisance caused by particles and electrostatic charge generated during shipping. SAMPLES: Due to the nature of this product line, free samples are not available, unless they are against an existing firm order, pending qualification of a process. HTE LABS guarantees continuous supply and availability of any of it's standard or custom developed processes and technologies provided minimum order quantities are met. HTE LABS has made every effort to have this information as accurate as possible. However, no responsibility is assumed by HTE LABS for its use, nor for any infringements of rights of third parties, which may result from its use. HTE LABS reserves the right to revise the content or modify its product line without prior notice. HTE LABS processes and technologies are not authorized for and should not be used within support systems which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without HTE LABS specific written consent. Home>Silicon Thermal Oxidation>Last updated: HTE LABSwww.htelabs.com Tel:(408)986-8026 Fax:(408)986-8027HTE LABS Display settings for best viewing:Current display settings: Screen resolution: 1024x768Screen resolution: Color quality: 16 bitColor quality: bit 1990- HTE LABS All rights reserved. No material from this site may be used or reproduced without permission.
 

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CUSTOM SILICON THERMAL WET OXIDATION PROCESS
HTE Labs

 

PROPERTIES / FEATURES   APPLICATIONS
Chemical Composition=SiO2   Passivation of junctions, protection of silicon surface.
Refractive Index=1.462   Gate dielectric for MOS FETS, dielectric for MOS Capacitors.
Dielectric Constant=3.4   Masking layer during dopant predeposition and diffusion.
Uniformity=5% to 10%   Masking layer during Ion Implantation process.
SiO2 Color chart and calculators HTE AN101 and HTE AN104   Insulation between conductors and silicon surface.
More properties @ HTE LABS APP NOTES   Etch stop, sacrificial layer, Ion Implant screen layer, MEMS, etc.

SHORT PROCESS DESCRIPTION
Silicon thermal oxidation processes are available only for prime wafers, delivered in sealed containers [original manufacturer seal must be present]. This is a high temperature process and wafers should be free of any photoresist or organic contamination. HTE Labs acceptance of customer supplied wafers is conditional, pending customer full disclosure of substrate composition, layer by layer, last process step or last cleaning process. For wafers supplied by HTE Labs, a standard chemical cleaning process may include RCA Clean as well as HF Dipped prior to final DI water rinse and spindry. As a standard procedure, wafers are loaded in quartz tubes at 600C and are unloaded after a ramp down also at 600C. Silicon wet thermal oxidation is performed in an atmosphere of H2, O2 Pyrogenic generated steam. Minim temperature is 900°C.

WAFER FOUNDRY - R&D SEMICONDUCTOR PROCESS DEVELOPMENT
HTE LABS is helping customers to solve R&D problems, capacity problems, lower cost as well as develop a back-up process for existing in-house operations. Any company currently involved or contemplating R&D related to semiconductor devices or thin film technologies, is encouraged to consider using HTE LABS expertise and capabilities. To contact HTE LABS and discuss an application in the strictest confidentiality, navigate to CONTACT PAGE.

PROCESS ORDERING INFORMATION

SI ORIENTATION WAFER SIZE
[mm]
TEMPERATURE
[°C]
THICKNESS
[nm]
TIME
[hours]

Process parametter TIME is calculated using Stanford SUPREM 4 software for the <100> and <111> orientation and for low doping levels as the worst case scenario. Actual oxidation TIME may vary. HTE Labs whenever feasible is tailoring each process to the actual orientation and doping levels such that the end thickness is within specified tolerance. Due to these factors, for Wet Oxidation processes oxide thickness tolerance is +/-5% to 10%.

STANDARD PROCESS PRICE LIST

PROCESS CODE ORIENTATION WAFER SIZE
[mm]
TEMPERATURE
[°C]
THICKNESS
[nm]
TIME
[h]
MINIM ORDER
[wafers]
UNIT PRICE
[$]
[100][W100][WTOX1100C][1000NM] 100 100 1100 1000 2.351 25 13.100    
 
Minimum batch for thermal oxidation is 25 wafers and maximum is 50 wafers depending on the wafer size and equipment availability at the time of RFQ. Unit price does not include SET-UP Charges, RUSH charges or cost of wafers.

INSTANT QUOTE
PROCESS CODE QTY EMAIL  
 
ORDERING: Registered customers can order online from within assigned BUSINESS PORTAL. A copy of the order along with an order confirmation receipt is issued instantly for all orders placed on line. On line Orders have to be verified, accepted and acknowledged by HTE LABS sales department in writing before, becoming non cancelable binding contracts.
DELIVERY: Typical delivery for Standard processes is 2-4 working days ARO. For Custom processes lead time may vary. HTE Labs may supply on request substrate materials from its own inventory or from third party supplier.
SHIPPING & PACKING: For certain processes, customer should ship only prime wafers, delivered in sealed containers [original manufacturer seal must be present]. All wafers shipped to HTE LABS by customers, should be packed in suitable wafer carriers or wafer containers, wrapped in reusable minim 2 layers of air bubble packing material [pink anti-static bubble cushioning wrap], or air pillows and heavy wall cardboard boxes. Foam packing peanuts are not acceptable due to the nuisance caused by particles and electrostatic charge generated during shipping.
SAMPLES: Due to the nature of this product line, free samples are not available, unless they are against an existing firm order, pending qualification of a process.
HTE LABS guarantees continuous supply and availability of any of it's standard or custom developed processes and technologies provided minimum order quantities are met.
HTE LABS has made every effort to have this information as accurate as possible. However, no responsibility is assumed by HTE LABS for its use, nor for any infringements of rights of third parties, which may result from its use. HTE LABS reserves the right to revise the content or modify its product line without prior notice. HTE LABS processes and technologies are not authorized for and should not be used within support systems which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without HTE LABS specific written consent.

Home>Silicon Thermal Oxidation> Last updated: July 06, 2009

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